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6.2.5
IRQ Status Register (IRQR)
Bit :
7
—
Initial value :
0
—
R/W :
Note: * Only 0 can be written, to clear the flag.
IRQR is an 8-bit readable/writable register that indicates the status of IRQ5 to IRQ0 interrupt
requests.
IRQR is initialized to H'00 by a reset.
Bit 7 and 6: Reserved
Do not write 1 to them.
Bits 5 to 0: IRQ5 to IRQ0 Flags
These bits indicate the status of IRQ5 to IRQ0 interrupt requests.
Bit n
IRQnF
Description
0
[Clearing conditions]
Cleared by reading IRQnF set to 1, then writing 0 in IRQnF
When IRQn interrupt exception handling is executed
1
[Setting conditions]
(1) When a falling edge occurs in
(IRQnEG = 0)
(2) When a rising edge occurs in
(IRQnEG = 0)
(3) When a falling or rising edge occurs in
set (IRQ0EG1 = 1)
Rev. 2.0, 11/00, page 104 of 1037
6
5
4
IRQ5F
IRQ4F
—
0
0
0
R/(W) *
R/(W) *
—
,54Q
,54Q
3
2
IRQ3F
IRQ2F
0
0
R/(W) *
R/(W) *
input while falling edge detection is set
input while rising edge detection is set
,54
input while both-edge detection is
1
0
IRQ1F
IRQ0F
0
0
R/(W) *
R/(W) *
(Initial value)
(n = 5 to 0)
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