Capstan Phase Error Detector; Overview; Block Diagram - Renesas Hitachi H8S/2194 Series Hardware Manual

28.9

Capstan Phase Error Detector

28.9.1

Overview

The capstan phase control system is required to start operation after the capstan motor has
arrived at the specified speed under the control of the speed control system. The capstan phase
control system operates in the following way in record/playback mode.
In record mode: Controls the tape running so that it may run at a specified speed together with
the speed control system.
In playback mode: Controls the tape running so that the recorded track may be traced correctly.
Any error deviated from the reference phase is detected by the digital counter. This phase error
data and the speed error data is processed and added by the digital filter circuit to control the
PWM output. The phase and speed of the capstan, in turn, is controlled by this PWM output.
The control signal of the capstan phase control in REC mode differs from that in PB mode. In
REC mode, the control is performed by the DVCFG2 signal which is generated by dividing the
frequencies of the reference signal (REF30P or CREF) and the CFG signal. In PB mode, it is
performed by divided rising signal (DVCTL) of the reference signal (CAPREF30) and the
playback control pulse (PB-CTL).
The reference signal in record and playback modes are as follows.
In record mode: 1/2 Vsync signal extracted from the video signal to be recorded
In playback mode: Signal generated by dividing the PB-CTL signal (DVCTL) at its rising edge
28.9.2

Block Diagram

Figure 28.34 shows the block diagram of the capstan phase error detector.
Rev. 2.0, 11/00, page 710 of 1037