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H'D058: Capstan Speed Error Detection Control Register
7
Bit :
CFCS1
CFCS0
0
Initial value :
R/W
R/W :
Clock source select bit
CFCS1 CFCS0
0
0
1
1
0
1
Notes:
1. Only 0 can be written.
2. When read, counter value is read.
Rev. 2.0, 11/00, page 928 of 1037
6
5
4
CFOVF
CFRFON CF-R/UNR CPCNT
0
0
0
*1
R/W
R/(W)
R/W
Capstan lock flag
Error data limit function select bit
0
Limit function OFF
1
Limit function ON
Counter overflow flag
0
Normal status
1
Counter overflows.
Description
φs
φs/2
φs/4
φs/8
CFVCR: Capstan Error Detector
3
2
CFRCS1
0
0
R
R/W
(R)/W
Capstan lock counter setting bit
CFRCS1 CFRCS0
0
1
Capstan phase system filter computation auto start bit
0
Filter computation by capstan lock detection is not excuted.
1
Filter computation of phase system is executed at the time of
drum lock detection.
0
Capstan speed system is not locked.
1
Capstan speed system is locked.
1
0
CFRCS0
0
0
*2
*2
(R)/W
Description
0
Underflow by 1 lock detection
1
Underflow by 2 lock detections
0
Underflow by 3 lock detections
1
Underflow by 4 lock detections
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