Renesas Hitachi H8S/2194 Series Hardware Manual page 257

Table 10.4 External Clock Output Settling Delay Time
(Conditions: V = 4.0 V to 5.5 V, AV
CC
Item
External clock output settling
delay time
Note: t includes 20 t
*
DEXT
4.0 V
V
CC
OSC1
(Internal)
RES
Note: * t includes 20 t
DEXT
Figure 10.7 External Clock Output Settling Delay Timing
Rev. 2.0, 11/00, page 230 of 1037
= 4.0 V to 5.5 V, V
CC
Symbol Min
t 500
*
DEXT
# $
of pulse width (t
CYC
t
DEXT
of RES pulse width (t
cyc
= AV
SS
Max

).
RESW
*
).
RESW
= 0 V)
SS
Unit Notes
µs
Figure 10.7