Renesas Hitachi H8S/2194 Series Hardware Manual page 625

(2) When the condition is not satisfied by Bcc instruction (8-bit displacement)
If the trap address is the next instruction to the Bcc instruction and the condition is not
satisfied by the Bcc instruction and thus it fails to branch, transition is made to the address
trap interrupt after executing the trap address instruction and prefetching the next instruction.
The address to be stacked is 02A2.
pre-fetch
Address bus
Interrupt
request
signal
Figure 27.7 When the Condition is Not Satisfied by Bcc Instruction (8-bit Displacement)
Rev. 2.0, 11/00, page 598 of 1037
BEQ NOP CMP NOP
instruc- instruc- instruc- instruc-
tion tion tion tion
pre-fetch pre-fetch pre-fetch
029E 02A0 02A8 02A2
BEQ NOP
execu- execu-
tion tion
Start of
exception
handling
*
02A4
NEXT:
(NEXT = H'02A8)
029E BEQ NEXT:8
02A0 NOP
02A2 NOP
02A4 NOP
02A6 NOP
02A8 CMP.W R0, R1
02AA NOP
* Trap setting address
The underlines address is the
one to be actually stacked.