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25.2.8 Module Stop Control Register (MSTPCR) ....................................................... 545
25.3 Operation..................................................................................................................... 546
2
25.3.1 I
C Bus Data Format........................................................................................ 546
25.3.2 Master Transmit Operation .............................................................................. 547
25.3.3 Master Receive Operation................................................................................ 550
25.3.4 Slave Receive Operation.................................................................................. 553
25.3.5 Slave Transmit Operation ................................................................................ 556
25.3.6 IRIC Setting Timing and SCL Control ............................................................. 558
25.3.7 Noise Canceler ................................................................................................ 560
25.3.8 Sample Flowcharts .......................................................................................... 560
25.3.9 Initialization of Internal State........................................................................... 565
25.4 Usage Notes................................................................................................................. 567
Section 26 A/D Converter.............................................................................. 573
26.1 Overview..................................................................................................................... 573
26.1.1 Features........................................................................................................... 573
26.1.2 Block Diagram ................................................................................................ 574
26.1.3 Pin Configuration ............................................................................................ 575
26.1.4 Register Configuration..................................................................................... 576
26.2 Register Descriptions ................................................................................................... 577
26.2.1 Software-Triggered A/D Result Register (ADR) .............................................. 577
26.2.2 Hardware-Triggered A/D Result Register (AHR) ............................................. 577
26.2.3 A/D Control Register (ADCR)......................................................................... 579
26.2.4 A/D Control/Status Register (ADCSR) ............................................................ 582
26.2.5 Trigger Select Register (ADTSR) .................................................................... 585
26.2.6 Port Mode Register 0 (PMR0) ......................................................................... 585
26.2.7 Module Stop Control Register (MSTPCR) ....................................................... 586
26.3 Interface to Bus Master ................................................................................................ 587
26.4 Operation..................................................................................................................... 588
26.4.1 Software-Triggered A/D Conversion................................................................ 588
26.4.2 Hardware- or External-Triggered A/D Conversion ........................................... 589
26.5 Interrupt Sources.......................................................................................................... 590
Section 27 Address Trap Controller (ATC).................................................... 591
27.1 Overview..................................................................................................................... 591
27.1.1 Features........................................................................................................... 591
27.1.2 Block Diagram ................................................................................................ 591
27.1.3 Register Configuration..................................................................................... 592
27.2 Register Descriptions ................................................................................................... 592
27.2.1 Address Trap Control Register (ATCR) ........................................................... 592
27.2.2 Trap Address Register 2 to 0 (TAR2 to TAR0) ................................................ 593
27.3 Precautions in Usage.................................................................................................... 595
27.3.1 Basic Operations ............................................................................................. 595
Rev. 2.0, 11/00, page xiv of xviii
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