Renesas Hitachi H8S/2194 Series Hardware Manual page 948

H'D028: Drum System Digital Filter Control Register DFIC: Digital Filter
Bit : 7
1
Initial value :
R/W :
Drum system range over flag
0
1
Note: * Only 0 can be written.
6 5
DROV DPHA DZPON
0 0
R/(W) *
R/(W) R/W
Drum phase system Z
0 Phase system Z
1 Phase system Z
Drum phase system filter computation start bit
0 Phase system filter computation is OFF.
Phase system computation result Y is not added to Es.
1 Phase system filter computation is ON.
Filter computation result does not exceed 12 bits.
Filter computation result exceeds 12 bits.
4 3 2
DZSON DSG2
0 0 0
R/W R/W
Drum system gain control bit
DSG2 DSG1 DSG0
0 0
1
1 0
1
Note: * Optional
-1
Drum speed system Z initialization bit
-1
0 Speed system Z reflects DZs value.
-1
1 Speed system Z does not relect DZs value.
-1
initialization bit
-1
reflects DZp value.
-1
does not relect DZp value.
Rev. 2.0, 11/00, page 921 of 1037
1 0
DSG1 DSG0
0 0
R/W R/W
Description
0 x 1
1 x 2
0 x 4
1 x 8
0 x 16
1 (x 32) *
0 (x 64) *
1 Invalid (do not set)