Renesas Hitachi H8S/2194 Series Hardware Manual page 769

Bit 4
HMSK Description
0 OSCH is added in
1 OSCH is not added in
Bit 3: High Impedance Bit (HiZ)
Set to 1 when the intermediate level is generated by an external circuit.
Bit 3
HiZ Description
0 Vpulse is a three-level output pin
1 Vpulse is a three-state output pin (high, low, or high-impedance)
Bits 2 to 0: Additional V Output Control Bit (CUT, VPON, POL)
These bits control the output at the additional V pin.
Bit 2 Bit 1
CUT VPON
0 0
1
1 *
Note: Don't care.
*
Rev. 2.0, 11/00, page 742 of 1037
Bit 0
POL Description
Low level
*
0 Negative polarity (see figure 28.46)
1 Positive polarity (see figure 28.45)
0 Intermediate level (high impedance if HiZ bit = 1)
1 High level
(Initial value)
(Initial value)
(Initial value)