Renesas Hitachi H8S/2194 Series Hardware Manual page 7

Page Item
166
7.8.9 Programmer Mode
Transition Time
169
7.10 Note on Switching from
F-ZTAT Version to Mask ROM
Version

Section 8 ROM (H8S/2194C
Series)
221 9.1 Overview
304 14.1.2 Block Diagram
308 14.2.1 Timer Mode Register J
(TMJ)
311, 312 14.2.2 Timer J Control
Register (TMJC)
336
16.2.1 Timer R Mode
Register 1 (TMRM1)
416 20.2.1 12-Bit PWM Control
Registers (CPWCR, DPWCR)
419 20.2.2 12-Bit PWM Data
Registers (CPWDR, DPWDR)
420
20.2.3 Module stop Control
Register (MSTPCR)
443 23.1.2 Block Diagram
454
23.2.7 Serial Status Register
(SSR1)
520 25.1.4 Register Configuration Table 25.2 Register Configuration
522 25.2.1 I
(ICDR)
531, 25.2.5 I
534 to 536 Register (ICCR)
541 25.2.6 I
Register (ICSR)
544 25.2.7 Serial/Timer Control
Register (STCR)
2
C Bus Data Register
2
C Bus Control
2
C Bus Status
Revisions (See Manual for Details)
Figure 7.23 Oscillation Stabilization Time, Boot
Program Transfer Time, and Power Supply Fall
Sequence
Vcc timing amended
Added
Added
Description amended due to introduction of the
H8S/2194C series
Figure 14.1 Block Diagram of the Timer J
φ/1024 clock source (for H8S/2194C series) added
Bits 3 and 2
Description amended
Bit 0 description amended
Bit 0 description amended
Initialization description amended
Initialization description amended
Added
Figure 23.1 Block Diagram of SCI1
Register names amended
Bit 7:
Clearing conditions amended
Note 2 description amended
Description amended
Bit 7 description amended
Bit 1 description amended
Bit 4 description amended
Bit 5 description amended
Rev. 2.0, 11/00, page III of V