Table of Contents
Advertisement
H'D09A: DVCFG Control Register CDVC: Frequency Divider
Bit :
7
MCGin
Initial value :
0
R/W *
R/W :
Mask CFG flag
0 CFG normal operation
1 DVCFG is detected while mask is set (race detection)
Note: * Only 0 can be written
H'D09B: CFG Frequency Division Register 1 CDIVR1: Frequency Divider
Bit :
7
—
Initial value :
1
—
R/W :
H'D09C: CFG Frequency Division Register 2 CDIVR2: Frequency Divider
Bit :
7
—
Initial value :
1
—
R/W :
Rev. 2.0, 11/00, page 946 of 1037
6
5
4
—
CMK
CMN
1
1
0
—
R
W
CFG mask select bit
0 Capstan mask timing function ON
1 Capstan mask timing function OFF
CFG mask status bit
0 Mask is released by capstan mask timer
1 Mask is set by capstan mask timer
6
5
CDV16
CDV15
CDV14
0
0
W
W
6
5
CDV26
CDV25
CDV24
0
0
W
W
3
2
DVTRG
CRF
0
0
W
W
CFG mask timer clock select bit
CFG frequency division edge select bit
0 Execute frequency division operation at CFG rising edge
1 Execute frequency division operation at CFG rising
and falling edges
PB (ASM)-to-REC transition timing sync ON/OFF select bit
0 PB (ASM)-to-REC transition timing sync ON
1 PB (ASM)-to-REC transition timing sync OFF
4
3
2
CDV13
CDV12
0
0
0
W
W
W
4
3
2
CDV23
CDV22
0
0
0
W
W
W
1
0
CPS1
CPS0
0
0
W
W
CPS1
CPS0 Description
φs/1024
0
0
φs/512
1
φs/256
1
0
φs/128
1
1
0
CDV11
CDV10
0
0
W
W
1
0
CDV21
CDV20
0
0
W
W
Advertisement
Table of Contents
