Timer J Control Register (Tmjc) - Renesas Hitachi H8S/2194 Series Hardware Manual

14.2.2

Timer J Control Register (TMJC)

Bit :
BUZZ1
Initial value :
R/W : R/W
Note: * Bit 0 is readable/writable only in the H8S/2194C series.
The timer J control register works to select the buzzer output frequency and to control
permission/prohibition of interrupts.
The TMJC is an 8-bit read/write register.
When reset, the TMJC is initialized to H'09.
Bits 7 and 6: Selecting the Buzzer Output (BUZZ1 or BUZZ0)
This bit works to select if using the buzzer outputs as the output signal through the BUZZ pin or
if using the monitor signals as the output signal through the BUZZ pin.
When setting is made to the monitor signals, choose the monitor signal using the MON1 bit and
MON0 bit.
Bit 7 Bit 6
BUZZ1 BUZZ0
0 0
1
1 0
1
Rev. 2.0, 11/00, page 310 of 1037
7 6 5
BUZZ0 MON1
0 0 0
R/W R/W
Description
φ/4096
φ/8192
Works to output monitor signals
Works to output BUZZ signals from the Timer J
4 3
—
MON0 TMJ2IE
0 1
—
R/W R/W
(Initial value)
2 1 0
(PS22) *
TMJ1IE
0 0 1
(R/W) *
R/W
Frequency when
φ = 10MHz
2.44 kHz
1.22 kHz