Renesas Hitachi H8S/2194 Series Hardware Manual page 581

Start condition
issurance
SCL
(Master output)
SCL
(Slave output)
SDA
(Master output)
SDA
(Slave output)
RDRF
IRIC
ICDRS
ICDRR
User processing
Figure 25.9 Example of Timing in Slave Receive Mode (MLS = ACKB = 0) (1)
Rev. 2.0, 11/00, page 554 of 1037
1 2 3 4
Bit 7 Bit 6 Bit 5 Bit 4
Slave address
5 6 7 8
Bit 3 Bit 2 Bit 1 Bit 0
R/W
[5] Read ICDR
9 1 2
Bit 7 Bit 6
Data 1
[4]
A
Interrupt request
generated
Address + R/W
Address + R/W
[5] Clear IRIC