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28.4.7
Interrupt
The HSW timing generator generates an interrupt under the following conditions.
(1) IRRHSW1 occurred when pattern data was written (OVWA, OVWB = 1) and FIFO was full
(FULL).
(2) IRRHSW1 occurred when matching was detected and the STRIG bit of FIFO was 1.
(3) IRRHSW1 occurred when the values of the 16-bit timer counter and 16-bit timing pattern
register matched.
(4) IRRHSW2 occurred when the 16-bit timer counter was cleared.
(5) IRRHSW2 occurred when a VD signal (capture signal of the timer capture register) was
received in PB mode.
(2) and (3), as well as (4) and (5), are switched over by ISEL1 and ISEL2.
Rev. 2.0, 11/00, page 675 of 1037
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