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H'D038: Drum Speed Error Detection Control Register DFVCR: Drum Error Detector
Bit :
7
DFCS1
DFCS0
Initial value :
0
R/W
R/W :
Clock source select bit
DFCS1 DFCS0
0
0
1
1
0
1
1. Only 0 can be written.
Notes:
2. When read, counter value is read.
6
5
4
DFOVF
DFRFON DF-R/UNR
0
0
0
1
R/W
R/(W)
*
R/W
Drum lock flag
Error data limit function select bit
0
Limit function OFF
1
Limit function ON
Counter overflow flag
0
Normal status
1
Counter overflows.
Description
φs
φs/2
φs/4
φs/8
3
2
DPCNT
DFRCS1
0
0
R
R/W
(R)/W
Drum lock counter setting bit
DFRCS1 DFRCS0
0
1
Drum phase system filter computation auto start bit
0
Filter computation by drum lock detection is not excuted.
1
Filter computation of phase system is executed at the time of
drum lock detection.
0
Drum speed system is not locked.
1
Drum speed system is locked.
1
0
DFRCS0
0
0
2
2
*
(R)/W
*
Description
0
Underflow by 1 lock detection
1
Underflow by 2 lock detections
0
Underflow by 3 lock detections
1
Underflow by 4 lock detections
Rev. 2.0, 11/00, page 925 of 1037
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