Description Of Operation - Renesas Hitachi H8S/2194 Series Hardware Manual

Bit 4: Preset Signal Selection Bit (CR/RF)
Selects the preset signal.
Bit 4
CR/RF Description
0 Presets REF30P signal
1 Presets CREF signal
Bit 3: Preset and Latch Signal Selection Bit (SELCFG2)
Selects the counter preset signal and the error data latch signal data in PB (ASM) mode.
Bit 3
SELCFG2 Description
0 Presets CAPREF30 signal; latches DVCTL signal
1 Presets REF30P (CREF) signal; latches DVCFG2 signal
Bits 2 to 0: Reserved
No read or write is valid.
28.9.5

Description of Operation

The capstan phase error detector detects the phase error based on the reference value set in the
capstan specified phase preset data register 1 and 2 (CPPR1, CPPR2). The reference values set
in CPPR1 and CPPR2 are preset in the counter by the REF30P (CREF) signal or CAPREF30
signal, and counted up by the clock selected. The latching of the error data is performed by
DVCTL or DVCFG2.
The error data detected in the error data automatic transmission mode (CFEPS bit of DFUCR =
0) is sent to the digital filter circuit automatically. In software transmission mode (CFEPS bit of
DFUCR = 1), the data written in CPER1 and CPER2 is sent to the digital filter circuit. The error
data is signed binary. It takes a positive number (+) if the phase is behind the specified phase, a
negative number (-) if in advance of the specified phase, or 0 if it had no phase error (revolving
at the specified phase). Figures 28.35 and 28.36 show examples of operation to detect a capstan
phase error.
(a) Capstan phase error detection counter
The capstan phase error detection counter stops the counter when overflow or latch occurred.
At the same time, it generates an interrupt request (IRRCAP3), setting the overflow flag
(CPOVF) if overflow occurred. Clear CPOVF by writing 0 after reading 1. If setting the
flag and writing 0 take place simultaneously, the latter is nullified.
Rev. 2.0, 11/00, page 716 of 1037
(Initial value)
(Initial value)