Operation - Renesas Hitachi H8S/2194 Series Hardware Manual

28.13.6 Operation

(a) CTL circuit operation
As shown in figure 28.49, the CTL discrimination/record circuit is composed of a 16-bit
up/down counter and 12-bit registers (×5).
In playback (PB) mode, the 16-bit up/down counter counts on a φs/4 clock when the PB-CTL
pulse is high, and on a φs/5 clock when low. In record (REC) or slow mode, this counter
counts up on a φs/8 clock when the pulse is high, and on a φs/4 clock when low.
This counter always counts up in record and slow modes.
In playback or slow mode, it is cleared on the rise of a PB-CTL signal. In record mode, it is
cleared on the rise of an REF30X signal.
UP
s/4
( s/8)
s/5
( s/4)
UDF:
Underflows when PB-CTL
duty is 43% or less
(b) CTL mode register (CTLM) switchover timing
CTLM is enabled immediately after data is written to the register. Care must be taken with
changes in the operating state.
Capstan phase control is performed by the VD sync REF30X (X-value + tracking value) and
PB-CTL in ASM mode, and by the REF30X or CREF and CFG division signal (DVCFG2) in
REC mode. If the CAPREF30 signal to be used for capstan phase control is always
generated by XDR, the value of XDR must be overwritten when switching between PB and
REC modes. Figures 28.50 and 28.51 show examples of switchover timing of CTLM and
XDR.
UP/DOWN control signal
REC: UP
PB, ASM:
UP when PB-CTL is high
Down when PB-CTL is low
UP/DOWN counter (16 bits)
DOWN
RCDR1
RCDR2
RCDR3
RCDR4
RCDR5
12-bit register
Figure 28.49 CTL Discrimination/Record Circuit
Counter clear signal
REF30X (REC)
PB-CTL (PB, ASM)
UDF
Duty
detection
Upper 12 bits
Match
REC-CTL
detection
Match
REC-CTL (S1)
detection
Match
REC-CTL (L1and ASM)
detection
Match
REC-CTL (S0)
detection
Match
REC-CTL (L0)
detection
Rev. 2.0, 11/00, page 763 of 1037