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Thus the receive margin in asynchronous mode is given by equation (1) below.
1
) − (L−0.5) F −
M = (0.5−
2N
Where M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in equation (1), a receive margin of 46.875% is given by
equation (2) below.
When D = 0.5 and F = 0,
1
M =(0.5−
2 × 16
=46.875%
However, this is only a theoretical value, and a margin of 20% to 30% should be allowed in
system design.
D − 0.5
N
) × 100%
(1+F) × 100%
Rev. 2.0, 11/00, page 497 of 1037
.....(1)
.....(2)
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