Erase Block Registers 1 (Ebr1); Erase Block Registers 2 (Ebr2) - Renesas Hitachi H8S/2194 Series Hardware Manual

8.3.3

Erase Block Registers 1 (EBR1)

7
Bit :
EBR1 : —
0
Initial value :
—
R/W :
EBR1 is a register that specifies the flash memory erase area block by block. EBR1 is
initialized to H'00 by a reset, in power-down state (excluding the medium-speed mode, module
stop mode, and sleep mode), when a low level is input to the FWE pin, or when a high level is
input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set, the
corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1
or EBR2 (more than one bit cannot be set).
The flash memory block configuration is shown in table 8.3.
8.3.4

Erase Block Registers 2 (EBR2)

Bit :
7
EBR2 :
EB7
Initial value :
0
R/W :
R/W
EBR2 is a register that specifies the flash memory erase area block by block. EBR2 is
initialized to H'00 by a reset, in power-down state (excluding the medium-speed mode, module
stop mode, and sleep mode), when a low level is input to the FWE pin, or when a high level is
input to the FWE pin and the SWE bit in FLMCR1 is not set. When a bit in EBR2 is set, the
corresponding block can be erased. Other blocks are erase-protected. Set only one bit in EBR1
or EBR2 (more than one bit cannot be set).
The flash memory block configuration is shown in table 8.4.
6 5
— EB13 EB12
0 0
— R/W R/W
6 5
EB6 EB5 EB4
0 0
R/W R/W R/W
4 3 2
EB11 EB10
0 0 0
R/W R/W
4 3 2
EB3 EB2
0 0 0
R/W R/W
Rev. 2.0, 11/00, page 185 of 1037
1 0
EB9 EB8
0 0
R/W R/W
1 0
EB1 EB0
0 0
R/W R/W