Renesas Hitachi H8S/2194 Series Hardware Manual page 6

Page Item
134
7.3.2 Flash Memory Control
Register 2 (FLMCR2)
136 7.3.3 Erase Block Registers 1
and 2 (EBR1, EBR2)
138 7.4 On-Board Programming
Modes
140 7.4.1 Boot Mode
141
142
145 7.5.1 Program Mode
146 7.5.2 Program-Verify Mode
148 7.5.3 Erase Mode
7.5.4 Erase-Verify Mode
150 7.6.1 Hardware Protection
152 7.6.3 Error Protection
153
7.7 Interrupt Handling when
Programming/Erasing Flash
Memory
154 7.8.2 Socket Adapters and
Memory Map
Rev. 2.0, 11/00, page II of V
Revisions (See Manual for Details)
Description amended
The ESU and PSU bits are cleared to 0 in power-
down state (excluding the medium-speed mode,
module stop mode, and sleep mode), hardware
protect mode, and software protect mode.
Description amended
EBR1 and EBR2 are each initialized to H'00 by a
reset, in power-down state (excluding the medium-
speed mode, module stop mode, and sleep mode),
when a low level is input to the FWE pin, or when a
high level is input to the FWE pin and the SWE bit in
FLMCR1 is not set.
Table 7.4 Flash Memory Erase Blocks
EB3 address amended
Table 7.5 Setting On-Board Programming Modes
MD0 pin level in use program mode amended
Figure 7.8 Boot Mode Execution Procedure
Flow amended
Table 7.6 System Clock Frequencies for which
Automatic Adjustment of This LSI Bit Rate is
Possible
2400-bps transfer bit rate deleted
Figure 7.10 RAM Areas in Boot Mode
Programming control program area amended
Description amended
(For details, see the flowchart in figure 7.12.)
Description amended
(For details, see the flowchart in figure 7.12.)
Description amended
(For details, see the flowchart in figure 7.13.)
Description amended
(For details, see the flowchart in figure 7.13.)
Table 7.7 Hardware Protection
Reset/standby protection description amended
FLER bit setting condition (3) amended
Figure 7.14 Flash Memory State Transitions
amended
Note 1 amended
Table 7.9 Socket Adapter Product Codes
amended