H'D09D: DVCFG Mask Interval Register CTMR: Frequency Divider
Bit :
7
—
1
Initial value :
—
R/W :
H'D09E: FG Control Register FGCR: Frequency Divider
7
Bit :
—
Initial value :
1
R/W :
—
H'D0A0: Servo Port Mode Register SPMR: Servo Port
Bit :
7
CTLSTOP
Initial value :
0
R/W
R/W :
CTLSTOP bit
0 CTL circuit operates
1 CTL circuit does not operate
6
5
—
CPM5
1
1
—
W
6
5
—
—
1
1
—
—
6
5
4
—
CFGCOMP
EXCTLON DPGSW
1
0
0
R/W
R/W
—
DPG pin functionswitch bit
0 Separate input for drum control system input
1 Weight input for drum control system input
EXCTL pin function switch bit
0 EXCTL/PS4 pin functions as EXCEL input pin
1 EXCTL/PS4 pin functions as PS4 I/O pin
CFG input method switch bit
0 Zero cross type comparator method for CFG signal input
1 Digital signal input method for CFG signal input
4
3
CPM4
CPM3
1
1
W
W
4
3
—
—
1
1
—
—
DFG edge select bit
0 NCDFG signal rising edge is selected
1 NCDFG signal falling edge is selected
3
2
1
COMP
H.Amp.SW
0
0
0
R/W
R/W
R/W
H.AmpSW pin function switch bit
0 H.AmpSW/PS1 pin functions as H.AmpSW output pin
1 H.AmpSW/PS1 pin functions as PS1 I/O pin
COMP pin function switch bit
0 COMP/PS2 pin functions as COMP input pin
1 COMP/PS2 pin functions as PS2 I/O pin
(DPG/PS3 pin functions as DPG input pin)
(DPG/PS3 pin functions as PS3 I/O pin)
2
1
CPM2
CPM1
1
1
W
W
2
1
0
—
—
DRF
1
1
0
W
—
—
0
C.Rot
0
R/W
C.Rotary pin function switch bit
0 C.Rotary/PS0 pin functions as C.Rotary output pin
1 C.Rotary/PS0 pin functions as PS0 I/O pin
Rev. 2.0, 11/00, page 947 of 1037
0
CPM0
1
W