Renesas Hitachi H8S/2194 Series Hardware Manual page 877

4.0V
Vcc
OSC1
(Internal)
RES
Note: *
The t
DEXT
Figure 29.13 External Clock Stabilization Delay Timing
Rev. 2.0, 11/00, page 850 of 1037
t
EXCLH
V
IH
X1
V
IL
t
EXCLr
Figure 29.12 Subclock Input Timing
t
DEXT
includes the RES pin Low level width 20 t
t
subcyc
t
EXCLL
Vcc 0.5
t
EXCLf
*
.
cyc