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(4) FIFO Output Pattern Register 1 (FPDRA)
Bit :
15
—
Initial value :
1
—
R/W :
Bit :
7
PPGA7
*
Initial value :
R/W :
W
Note: * Undetermined
FPDRA is a buffer register for the output pattern register of FIFO1. When the timing pattern is
written in FTPRA the output pattern data written in FPDRA is written at the same time to the
position pointed by the buffer pointer of FIFO1. Be sure to write the output pattern data in
FPDRA before writing it in FTPRA.
FPDRA is a 16-bit write-only register. Only a word access is valid. If a byte access is
attempted, resulting operation is not assured. No read is valid. If a read is attempted, an
undetermined value is read out. It is not initialized by a reset, stand-by or module stop,
accordingly be sure to write data before use.
Bit 15: Reserved
It cannot be written in or read out.
Bit 14: A/D Trigger A Bit (ADTRGA)
A signal for starting the A/D converter hardware.
Bit 13: S-TRIGA Bit (STRIGA)
A signal for generating an interrupt by pattern data. When STRIGA is selected by ISEL, pattern
data changes from 0 to 1, and thus generates an interrupt.
Bit 12: NarrowFFA Bit (NarrowFFA)
Controls the Narrow Video Head.
Bit 11: VideoFFA Bit (VFFA)
Controls the Video Head.
Bit 10: AudioFFA Bit (AFFA)
Controls the Audio Head.
Bit 9: VpulseA Bit (VpulseA)
Used for generating an additional V signal. See section 28.12, Additional V Signal Generator,
for more information.
14
13
ADTRGA
STRIGA
NarrowFFA
*
*
W
W
6
5
PPGA6
PPGA5
PPGA4
*
*
W
W
12
11
10
VFFA
AFFA
*
*
*
W
W
W
4
3
2
PPGA3
PPGA2
*
*
*
W
W
W
Rev. 2.0, 11/00, page 663 of 1037
9
8
VpulseA
MlevelA
*
*
W
W
1
0
PPGA1
PPGA0
*
*
W
W
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