Register Configuration; Register Descriptions - Renesas Hitachi H8S/2194 Series Hardware Manual

28.4.4

Register Configuration

Table 28.6 shows the register configuration of the HSW timing generator.
Table 28.6 Register Configuration
Name
HSW mode register 1
HSW mode register 2
HSW loop stage number setting
register
FIFO output pattern register 1
FIFO timing pattern register 1*
FIFO output pattern register 2
FIFO timing pattern register 2
DFG reference register 1*
DFG reference register 2
FIFO timer capture register*
DFG reference count register*
Note: FTPRA and FTCTR, as well as DFCRA and DFCTR, are allocated to the same
*
addresses.
28.4.5

Register Descriptions

(1) HSW Mode Register 1 (HSM1)
Bit :
7
FLB
Initial value :
0
R/W :
R
Note: * Only 0 can be written
HSM1 is a register which confirms and determines the operational state of the HSW timing
generator.
HSM1 is an 8-bit register. Bits 7 to 4 are read-only bits, and write is disabled. All the other bits
accept both read and write. It is initialized to H'30 by a reset or stand-by.
Abbrev. R/W
HSM1 R/W
HSM2 R/W
HSLP R/W
FPDRA W
FTPRA W
FPDRB W
FTPRB W
DFCRA W
DFCRB W
FTCTR R
DFCTR R
6 5
FLA EMPB EMPA
0 1
R R
Size
Byte
Byte
Byte
Word
Word
Word
Word
Byte
Byte
Word
Byte
4 3 2
OVWB OVWA
1 0 0
R/(W) * R/(W) *
R
Rev. 2.0, 11/00, page 653 of 1037
Initial Value Address
H'30 H'FD060
H'00 H'FD061
Undetermined H'FD062
Undetermined H'FD064
Undetermined H'FD066
Undetermined H'FD068
Undetermined H'FD06A
Undetermined H'FD06C
Undetermined H'FD06D
H'0000 H'FD066
H'E0 H'FD06C
1 0
CLRB CLRA
0 0
R/W R/W