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(3) Notes on Use of Boot Mode:
(a) When reset is released in boot mode, it measures the low period of the input at the SCI1's
SI1 pin. The reset should end with SI1 pin high. After the reset ends, it takes about 100
states for the chip to get ready to measure the low period of the SI1 pin input.
(b) In boot mode, if any data has been programmed into the flash memory (if all data is not
1), all flash memory blocks are erased. Boot mode is for use when user program mode is
unavailable, such as the first time on-board programming is performed, or if the program
activated in user program mode is accidentally erased.
(c) Interrupts cannot be used while the flash memory is being programmed or erased.
(d) The SI1 and SO1 pins should be pulled up on the board.
(e) Before branching to the programming control program (RAM area H'FFF3B0), the chip
terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing
the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The
transmit data output pin, SO1, goes to the high-level output state (P21PCR = 1, P21PDR
= 1).
The contents of the CPU's internal general registers are undefined at this time, so these
registers must be initialized immediately after branching to the programming control
program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls,
etc., a stack area must be specified for use by the programming control program.
The initial values of other on-chip registers are not changed.
(f) Boot mode can be entered by making the pin settings shown in table 8.6 and executing a
reset-start.
When the chip detects the boot mode setting at reset release
internally.
Boot mode can be cleared by driving the reset pin low, waiting at least 20 states, then
setting the FWE pin and mode pins, and executing reset release
cleared by a WDT overflow reset.
If the mode pin input levels are changed in boot mode, the boot mode state will be
maintained in the microcomputer, and boot mode continued, unless a reset occurs.
However, the FWE pin must not be driven low while the boot program is running or flash
memory is being programmed or erased
Notes: 1. Mode pin and FWE pin input must satisfy the mode programming setup time (t
states) with respect to the reset release timing.
2. For further information on FWE application and disconnection, see section 8.9, Flash
Memory Programming and Erasing Precautions.
*1
*2
.
Rev. 2.0, 11/00, page 193 of 1037
, it retains that state
*1
. Boot mode can also be
= 4
MDS
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