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8.5
Programming/Erasing Flash Memory
In the on-board programming modes, flash memory programming and erasing is performed by
software, using the CPU. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. For addresses H'00000 to H'1FFFF,
transitions to these modes can be made by setting the PSU1, ESU1, P1, E1, PV1 and EV1 bits in
FLMCR1 and for addresses H'20000 to H'3FFFF, transitions to these modes can be made by
setting the PSU2, ESU2, P2, E2, PV2 and EV1 bits in FLMCR2.
The flash memory cannot be read while being programmed or erased. Therefore, the program
that controls flash memory programming/erasing (the programming control program) should be
located and executed in on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU1, PSU1, EV1, PV1,
E1, and P1 bits in FLMCR1, and the ESU2, PSU2, EV2, PV2, E2 and P2 bits in
FLMCR2, is executed by a program in flash memory.
2. When programming or erasing, set FWE to 1 (programming/erasing will not be
executed if FWE = 0).
3. Perform programming in the erased state. Do not perform additional programming
on previously programmed addresses.
Do not program addresses H'00000 to H'1FFFF and H'20000 to H'3FFFF at the same
time. Operation is not guaranteed if both areas are programmed at the same time.
8.5.1
Program Mode (n = 1 for addresses H'0000 to H'1FFFF and n= 2 for addresses
H'20000 to H'3FFFF)
Follow the procedure shown in the program/program-verify flowchart in figure 8.12 to write
data or programs to flash memory. Performing program operations according to this flowchart
will enable data or programs to be written to flash memory without subjecting the device to
voltage stress or sacrificing program data reliability. Programming should be carried out 32
bytes at a time.
Table 29.9 in section 29.2.7, Flash Memory Characteristics, lists wait time (x, y, z, α, β, γ, ε and
η) after setting or clearing each bit on the flash memory control registers 1 and 2 (FLMCR1 and
FLMCR2) and the maximum write count (N).
Following the elapse of (x) µs or more after the SWE bit is set to 1 in flash memory control
register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram
data area, and the 32-byte data in the reprogram data area written consecutively to the write
addresses. The lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60, H'80,
H'A0, H'C0, or H'E0. Thirty-two consecutive byte data transfers are performed. The program
address and program data are latched in the flash memory. A 32-byte data transfer must be
performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the
extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway,
etc. Set more than (y + z + α + β) µs as the WDT overflow period. After this, preparation for
Rev. 2.0, 11/00, page 195 of 1037
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