Table of Contents
Advertisement
H'D0A4: CTL Gain Control Register CTLGR: Servo Port
Bit :
7
—
Initial value :
1
—
R/W :
H'D0B0: Vertical Sync Signal Threshold Value Register VTR: Sync Detector (Servo)
Bit :
7
—
Initial value :
1
—
R/W :
6
5
4
—
CTLE/A
CTLFB
1
0
0
—
R/W
R/W
CTL amp feedback SW bit
0 CTLFB SW is OFF
1 CTLFB SW is ON
CTL select bit
0 AMP output
1 EXCTL
6
5
4
—
VTR5
VTR4
1
0
0
—
W
W
3
2
CTLGR3
CTLGR2 CTLGR1
0
0
R/W
R/W
CTL amp gain setting bit
CTLGR3 CTLGR2 CTLGR1
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Note: * With a setting of 64.0dB or more, the CTLAMP is in a
very sensitive status. When configuring the set board,
be concerned about countermeasure against noise
around the control head signal input port.
Also, thoroughly set the filter between the CTLAMP
and CTLSMT.
3
2
VTR3
VTR2
0
0
W
W
Rev. 2.0, 11/00, page 949 of 1037
1
0
CTLGR0
0
0
R/W
R/W
CTLGR0 CTL outpu gain
0
34.0 dB
1
36.5 dB
0
39.0 dB
1
41.5 dB
0
44.0 dB
1
46.5 dB
0
49.0 dB
1
51.5 dB
0
54.0 dB
1
56.5 dB
0
59.0 dB
1
61.5 dB
64.0 dB *
0
66.5 dB *
1
69.0 dB *
0
71.5 dB *
1
1
0
VTR1
VTR0
0
0
W
W
Advertisement
Table of Contents
