Renesas Hitachi H8S/2194 Series Hardware Manual page 651

Bits 3 to 0: CTL Amplifier Gain Setting Bits (CTLGR3 to 0)
Set the output gain of the CTL amplifier.
Bit 3 Bit 2
CTLGR3 CTLGR2
0 0
1
1 0
1
Note: * With a setting of 64.0 dB or more, the CTLAMP is in a very sensitive status. When
configuring the set board, be concerned about countermeasure against noise around
the control head signal input port. Also, thoroughly set the filter between the CTLAMP
and CTLSMT.
Rev. 2.0, 11/00, page 624 of 1037
Bit 1 Bit 0
CTLGR1 CTLGR0
0 0
1
1 0
1
0 0
1
1 0
1
0 0
1
1 0
1
0 0
1
1 0
1
CTL Output Gain
34.0 dB
36.5 dB
39.0 dB
41.5 dB
44.0 dB
46.5 dB
49.0 dB
51.5 dB
54.0 dB
56.5 dB
59.0 dB
61.5 dB
64.0 dB*
66.5 dB*
69.0 dB*
71.5 dB*
(Initial value)