Renesas Hitachi H8S/2194 Series Hardware Manual page 830

(7) Sync Signal Control Register (SYNCR)
7
Bit :
—
Initial value :
1
—
R/W :
Note: * Only 0 can be written
SYNCR controls the noise detection, field detection, polarity of the sync signal input, etc.
SYNCR is an 8-bit register. It is initialized to H'F8 by a reset, stand-by or module stop. Bits
7 to 4 are reserved. No write is valid. Bit 1 is valid for read only.
Bits 7 to 4: Reserved
Writes are disabled. If a read is attempted, an undetermined value is read out.
Bit 3: Interrupt Selection Bit (NIS/VD)
Selects whether an interrupt request is generated when a noise level was detected or when the
VD signal was detected.
Bit 3
NIS/VD Description
0 Interrupt at the noise level
1 Interrupt at VD
Bit 2: Noise Detection Flag (NOIS)
NOIS is a status flag indicating that the noise counts reached at more than four times of the
value set in NDR. The flag is cleared only by writing 0 after reading 1. Care is required
because it is not cleared automatically.
Bit 2
NOIS Description
0 Noise count is smaller than four times of the value set in NDR
1 Noise count is equal to or greater than four times of the value set in NDR
6 5 4
— — —
1 1 1
— — —
3 2
NIS/VD NOIS
1 0
R/(W) *
R/W
Rev. 2.0, 11/00, page 803 of 1037
1 0
FLD SYCT
0 0
R R/W
(Initial value)
(Initial value)