28.14.4 Dfg Noise Removal Circuit - Renesas Hitachi H8S/2194 Series Hardware Manual

28.14.4 DFG Noise Removal Circuit

(1) Block Diagram
Figure 28.70 shows the block diagram of the DFG noise removal circuit.
DFG
(2) Register Descriptions
• Register configuration
Table 28.24 shows the register configuration of the DFG mask circuit.
Table 28.24 Register Configuration
Name
FG control register
• FG Control Register (FGCR)
Bit :
Initial value :
R/W :
Selects the edge of the DFG noise removal signal (NCDFG) to be sent to the drum speed error
detector. If a read is attempted, an undetermined value is read out. Bits 7 to 1 are reserved. No
write in them is valid.
It is initialized to H'FE by a reset, stand-by or module stop.
The edge selection circuit is located in the drum speed error detector, and outputs the register
output to the drum speed error detector.
Bits 7 to 1: Reserved
No write in them is valid. If a read is attempted, an undetermined value is read out.
Delay circuit
delay = 2
Figure 28.70 DFG Noise Removal Circuit
Abbrev.
FGCR
7 6 5
— — —
1 1 1
— — —
Edge
detection
Edge
detection
R/W Size
W Byte
4 3
— —
1 1
— —
S Q NCDFG
R
Initial Value
H'FE
2 1
— —
1 1
— —
Rev. 2.0, 11/00, page 793 of 1037
Address
H'FD09E
0
DRF
0
W