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Exception-handling state
RES = High
*1
Reset state
1.
From any state, a transition to the reset state occurs whenever RES goes low. A transition can
Notes:
also be made to the reset state when the watchdog timer overflows.
2.
The power-down state also includes a watch mode, subactive mode, subsleep mode, etc. For
details, see section 4, Power-Down State.
2.8.2
Reset State
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When the
input goes low all current processing stops and the CPU enters the reset state.
All interrupts are disabled in the reset state. Reset exception handling starts when the
signal changes from low to high.
The reset state can also be entered by a watchdog timer overflow. For details, see section 17,
Watchdog Timer.
Program execution state
External interrupt request
Figure 2.15 State Transitions
Sleep mode
Standby mode
*2
Power-down state
Rev. 2.0, 11/00, page 53 of 1037
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