Renesas Hitachi H8S/2194 Series Hardware Manual page 742

(3) Capstan Phase Error Detection Control Register (CPGCR)
Bit : 7
CPCS1
Initial value :
0
R/W
R/W :
Note: * Only 0 can be written
CPGCR controls the operation of capstan phase error detection.
CPGCR is an 8-bit readable/writable register. Bits 2 to 0 are reserved, bit 5 accepts only read
and 0 write.
It is initialized to H'07 by a reset or stand-by.
Bits 7 and 6: Clock Source Selection Bits (CPCS1, CPCS0)
Select the clock supplied to the counter. (φs = fosc/2)
Bit 7 Bit 6
CPCS1 CPCS0
0 0
1
1 0
1
Bit 5: Counter Overflow Flag (CPOVF)
CPOVF flag indicates the overflow of the 20-bit counter. It is cleared by writing 0. Write 0
after reading 1. Also, setting has the highest priority in this flag. If a flag set and 0 write occurs
simultaneously, the latter is nullified.
Bit 5
CPOVF Description
0 Normal state
1 Indicates that an overflow has occurred in the counter
6 5
CPCS0 CPOVF CR/RF
0 0
R/(W) *
R/W
Description
φs
φs/2
φs/4
φs/8
4 3
SELCFG2
0 0
R/W R/W
Rev. 2.0, 11/00, page 715 of 1037
2 1 0
— — —
1 1 1
— — —
(Initial value)
(Initial value)