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(6) REC-CTL Duty Data Register 4 (RCDR4)
Bit :
15
—
Initial value :
1
—
R/W :
RCDR4 sets the timing of falling edge of the 0 pulse (short) of REC-CTL in record or rewrite
mode. In detection mode, it is used to detect the long/short pulse.
RCDR4 is a 12-bit write-only register. It accepts only a word-access. If a byte access is
attempted, operation is not assured. If a read is attempted, an undefined value is read out. Bits
15 to 12 are reserved, and no write in them is valid.
It is initialized to H'F000 by a reset, stand-by, module stop or CTL stop.
In record mode, set a value with the 57.5% duty cycle obtained from the transition timing T4
corresponding to the servo clock frequency φs according to the following equation. See figure
28.60, REC-CTL Signal Generation Timing.
RCDR4 = T4 × φ s/64
φ is the servo clock frequency (= f
At bit pattern detection, set the 0 pulse long/short threshold value at REV. See figure 28.56,
Duty Discriminator.
RCDR4 = H'FFF − (T4' × φ s/80)
φs is the servo clock frequency (= f
at REV (s).
14
13
12
11
10
—
—
—
CMT4B
CMT4A
1
1
1
0
0
—
—
—
W
W
/2) in Hz, and T4 is the set timing (s).
OSC
/2) in Hz, and T4' is the 0 pulse long/short threshold value
OSC
9
8
7
6
5
CMT49
CMT48
CMT47
CMT46
CMT45
0
0
0
0
0
W
W
W
W
W
Rev. 2.0, 11/00, page 757 of 1037
4
3
2
1
0
CMT44
CMT43
CMT42
CMT41
CMT40
0
0
0
0
0
W
W
W
W
W
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