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Table 29.8 I
C Bus Interface Timing of HD64F2194, HD64F2194C
(Conditions: Vcc = AVcc = 4.0 to 5.5 V, Vss = AVss = 0.0 V, Ta = –20 to +75°C unless
otherwise specified.)
Item
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA input spike pulse
removal time
SDA input bus free time
Start condition input hold time
Re-transmit start condition
input setup time
Stop condition input setup time
Data input setup time
Data input hold time
SCL, SDA capacity load
Note:
1. Can also be set to 17.5 t
module.
Test
Symbol
Conditions
t
SCL
t
SCLH
t
SCLL
t
sr
t
sf
t
sp
t
BUF
t
STAH
t
STAS
t
STOS
t
SDAS
t
SDAH
C
b
depending on the selection of clock to be used by the I
cyc
Values
Min
Typ
Max
12
3
5
*1
7.5
300
1
5
3
3
3
0.5
0
400
Rev. 2.0, 11/00, page 833 of 1037
Unit
Figure
t
Figure
cyc
29.10
t
cyc
t
cyc
t
cyc
ns
t
cyc
t
cyc
t
cyc
t
cyc
t
cyc
t
cyc
ns
pF
2
C
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