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25.3.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data, and returns
an acknowledge signal. The slave device transmits data. I
the data buffers of ICDRR and ICDRS, so data can be received continuously in master receive
mode. For this construction, when stop condition issuing timing delayed, it may occurs the
internal contention between stop condition issuance and SCL clock output for next data
receiving, and then the extra SCL clock would be outputted automatically or the SCL line would
be held to low. And for I
data receiving, so the change timing of ACKB bit in ICSR should be controlled by software. To
take measures against these problems, the wait function should be used in master receive mode.
The reception procedure and operations with the wait function in master receive mode are
described below.
[1] Clear the TRS bit in ICCR to 0 to switch from transmit mode to receive mode, and set the
WAIT bit in ICMR to 1. Also clear the ACKB bit in ICSR to 0 (acknowledge data setting).
[2] When ICDR is read (dummy data read), reception is started, and the receive clock is output,
and data received, in synchronization with the internal clock. In order to detect wait
operation, set the IRIC flag in ICCR must be cleared to 0. After reading ICDR, clear IRIC
immediately not to execute other interrupt handling routine. If one frame of data has been
received before the IRIC clearing, it can not be determine the end of reception.
[3] The IRIC flag is set to 1 at the fall of the 8th receive clock pulse. If the IEIC bit in ICCR has
been set to 1, an interrupt request is sent to the CPU. SCL is automatically fixed low in
synchronization with the internal clock until the IRIC flag clearing. If the first frame is the
last receive data, execute step [10] to halt reception.
[4] Clear the IRIC flag to release from the Wait State. The master device outputs the 9th clock
and drives SDA at the 9th receive clock pulse to return an acknowledge signal.
[5] When one frame of data has been received, the IRIC flag in ICCR and the IRTR flag in ICSR
are set to 1 at the rise of the 9th receive clock pulse. The master device outputs SCL clock to
receive next data.
[6] Read ICDR.
[7] Clear the IRIC flag to detect next wait operation. From clearing of the IRIC flag to negation
of a wait as described in step [4] (and [9]) to clearing of the IRIC flag as described in steps
[5], [6], and [7], must be performed within the time taken to transfer one byte.
[8] The IRIC flags set to 1 at the fall of the 8th receive clock pulse. SCL is automatically fixed
low in synchronization with the internal clock until the IRIC flag clearing. If this frame is
the last receive data, execute step [10] to halt reception.
[9] Clear the IRIC flag in ICCR to cancel wait operation. The master device outputs the 9th
clock and drives SDA at the 9th receive clock pulse to return an acknowledge signal. Data
can be received continuously by repeating step [5] to [9].
Rev. 2.0, 11/00, page 550 of 1037
2
C bus interface system, the acknowledge bit must be set to 1 at the last
2
C bus interface module consists of
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