Renesas Hitachi H8S/2194 Series Hardware Manual page 365

Bit 2: Selection of Interrupt Causes (CP/SLM)
This bit works to select the interrupt causes for the TMRI3.
Bit 2
CP/SLM Description
0 Makes interrupt requests upon the capture signals of the TMRU-2 valid (Initial value)
1 Makes interrupt requests upon ending of the slow tracking mono-multi valid
Bit 1: Capture Signal Flag (CAPF)
This is a flag being set out by the capture signal of the TMRU-2. Although both reading/writing
are possible, 0 only is valid for writing.
Also, priority is being given to the set and, when the "capture signal" and "writing 0" occur
simultaneously, this flag bit remains being set to 1 and the interrupt request will not be issued
and it is necessary to be attentive about this fact.
When the CP/SLM bit (Bit 2) is being set to 1, this CAPF bit should always be set to 0.
The CAPF flag is cleared to 0 under the low power consumption mode.
Bit 1
CAPF Description
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
At occurrences of the TMRU-2 capture signals while the CP/SLM bit is being set to 0
Bit 0: Slow Tracking Mono-multi Flag (SLW)
This is a flag being set out when the slow tracking mono-multi processing ends. Although both
reading/writing are possible, 0 only is valid for writing.
Also, priority is being given to the set and, when "ending of the slow tracking mono-multi
processing" and "writing 0" occur simultaneously, this flag bit remains being set to 1 and the
interrupt request will not be issued and it is necessary to be attentive about this fact.
When the CP/SLM bit (Bit 2) is being set to 0, this SLW bit should always be set to 0.
The SLW flag is cleared to 0 under the low power consumption mode.
Bit 0
SLW Description
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
When the slow tracking mono-multi processing ends while the CP/SLM bit is being set
to 1
Rev. 2.0, 11/00, page 338 of 1037
(Initial value)
(Initial value)