Renesas Hitachi H8S/2194 Series Hardware Manual page 762

Bit 3: Capstan Phase System Error Data Transfer Bit (CFEPS)
Transfers the capstan phase system error data to the digital filter when the data write is enforced.
Bit 3
CFEPS Description
0 Error data is transferred by DVCFG2 signal latching
1 Error data is transferred when the data is written
Bit 2: Drum Phase System Error Data Transfer Bit (DFEPS)
Transfers the drum phase system error data to the digital filter when the data write is enforced.
Bit 2
DFEPS Description
0 Error data is transferred by HSW (NHSW) signal latching
1 Error data is transferred when the data is written
Bit 1: Capstan Speed System Error Data Transfer Bit (CFESS)
Transfers the capstan speed system error data to the digital filter when the data write is enforced.
Bit 1
CFESS Description
0 Error data is transferred by DVCFG signal latching
1 Error data is transferred when the data is written
Bit 0: Drum Speed System Error Data Transfer Bit (DFESS)
Transfers the drum speed system error data to the digital filter when the data write is enforced.
Bit 0
DFESS Description
0 Error data is transferred by NCDFG signal latching
1 Error data is transferred when the data is written
(Initial value)
(Initial value)
(Initial value)
(Initial value)
Rev. 2.0, 11/00, page 735 of 1037