Renesas Hitachi H8S/2194 Series Hardware Manual page 981

H'D0BA: Servo Interrupt Request Register 1 SIRQR1: Servo Interrupt
Bit : 7
IRRDRM3 IRRDRM2 IRRDRM1
0
Initial value :
R/(W) * R/(W) *
R/W :
Drum speed error detector (lock detection) interrupt request bit
0 Drum speed error detector (lock detection) interrupt request is not generated
1 Drum speed error detector (lock detection) interrupt request is generated
Drum phase error detector interrupt request bit
0 Drum phase error detector interrupt request is not generated
1 Drum phase error detector interrupt request is generated
Note: * Only 0 can be written to clear the flag.
Rev. 2.0, 11/00, page 954 of 1037
6 5 4
IRRCAP3 IRRCAP2 IRRCAP1 IRRHSW2 IRRHSW1
0 0 0
R/(W) * R/(W) *
Capstan speed error detector (lock detection) intrerrupt request bit
0 Capstan speed error detector (lock detection) interrupt request is not generated
1 Capstan speed error detector (lock detection) interrupt request is generated
Capstan phase error detector (OVF, latch) interrupt request bit
0 Capstan phase error detector (OVF, latch) interrupt request is not generated
1 Capstan phase error detector (OVF, latch) interrupt request is generated
Drum speed error detector (OVF, latch) interrupt request bit
0 Drum speed error detector (OVF, latch) interrupt request is not generated
1 Drum speed error detector (OVF, latch) interrupt request is generated
3 2 1
0 0 0
R/(W) * R/(W) * R/(W) *
HSW timing generator (OVW, match, STRIG)
interrupt request bit
HSW timing generator (counter clear, capture)
interrupt request bit
0 HSW timing generator (counter clear, capture) interrupt
request is not generated
0 HSW timing generator (counter clear, capture) interrupt
request is generated
Capstan speed error detector (OVF, latch) interrupt request bit
0 Capstan speed error detector (OVF, latch) interrupt request in not generated
1 Capstan speed error detector (OVF, latch) interrupt request in generated
0
0
R/(W) *
0 HSW timing generator (OVM, match, STRIG)
interrupt request is not generated
1 HSW timing generator (OVM, match, STRIG)
interrupt request is generated