Timer J Status Register (Tmjs) - Renesas Hitachi H8S/2194 Series Hardware Manual

Bit 0: Reserved (for H8S/2194 series)
When this is read, 1 will always be readout. Writes are disabled.
Bit 0: Selecting the Input clock for TMJ-2 (PS22) (for H8S/2194C series)
This bit, together with bits 3 and 2 (PS21, PS20) in TMJ, selects the input clock for TMJ-2. For
details, see section 14.2.1, Timer Mode Register J (TMJ).
14.2.3

Timer J Status Register (TMJS)

Bit :
TMJ2I
Initial value :
R/(W) *
R/W :
Note: * Only 0 can be written to clear the flag.
The timer J status register (TMJS) works to indicate issuance of the interrupt request of the
Timer J. The TMJS is an 8-bit read/write register. When reset, the TMJS is initialized to H'3F.
Bit 7: TMJ2I Interrupt Requesting Flag (TMJ2I)
This is the TMJ2I interrupt requesting flag. This flag is set when the TMJ-2 underflows.
Bit 7
TMJ2I Description
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
When the TMJ-2 underflows
Bit 6: TMJ1I Interrupt Requesting Flag (TMJ1I)
This is the TMJ1I interrupt requesting flag. This flag is set out when the TMJ-1 underflows.
TMJ1I interrupt requests will also be made under a 16-bit operation.
Bit 6
TMJ1I Description
0 [Clearing conditions]
When 0 is written after reading 1
1 [Setting conditions]
When the TMJ-1 underflows
Bits 5 to 0: Reserved
When they are read, 1 will always be readout. Writes are disabled.
Rev. 2.0, 11/00, page 312 of 1037
7 6 5
TMJ1I —
0 0 1
R/(W) *
—
4 3 2
— — —
1 1 1
— — —
1 0
— —
1 1
— —
(Initial value)
(Initial value)