Serial Control Status Register 2 (Scsr2) - Renesas Hitachi H8S/2194 Series Hardware Manual

Bits 4 and 3: Transmit Data Interval Select 1 and 0 (GAP1, GAP0)
When an internal clock is used, data can be transmitted at 1-byte intervals. During that time, the
SCK2 pin retains the high level. When data is transmitted without intervals, the STRB signal
retains the low level.
Bit 4 Bit 3
GAP1 GAP0
0 0
0 1
1 0
1 1
Bits 2 to 0: Transfer Clock Select 2 to 0 (CKS2 to CKS0)
Selects transfer clock.
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
24.2.4

Serial Control Status Register 2 (SCSR2)

7
Bit :
TEI
Initial value :
0
R/(W) *
R/W :
Note: * Only 0 can be written to clear the flag.
The SCSR2 is an 8-bit register that indicates the SCI2's state of operation and error.
The SCSR2 is initialized to H'60 by a reset.
Rev. 2.0, 11/00, page 504 of 1037
Description
Data transmission without intervals
Data intervals: 8 clocks
Data intervals: 24 clocks
Data intervals: 56 clocks
SCK2 Clock
pin source
SCK2 Prescaler
output S
SCK2 External
input clock
6 5
— —
1 1
— —
Prescaler division
ratio
φ/256 (Initial value)
φ/64
φ/32
φ/16
φ/8
φ/4
φ/2

4 3
SOL ORER WT
0 0
R/(W) * R/(W) *
R/W
(Initial value)
Transfer clock cycle
φ = 10 MHz φ = 5 MHz
25.6 µs 51.2 µs
6.4 µs 12.8 µs
3.2 µs 6.4 µs
1.6 µs 3.2 µs
0.8 µs 1.6 µs
0.4 µs 0.8 µs
 0.4 µs
 
2 1 0
ABT STF
0 0 0
R/(W) *
R/W