Subsleep Mode; Clearing Subsleep Mode - Renesas Hitachi H8S/2194 Series Hardware Manual

4.8

Subsleep Mode

4.8.1 Subsleep Mode
If a SLEEP instruction is executed in subactive mode when the SSBY in SBYCR is cleared to 0,
the LSON bit in LPWRCR is set to 1, and the TMA3 bit in TMA (Timer A) is set to 1, the CPU
makes a transition to subsleep mode.
In this mode, the CPU and all on-chip supporting modules other than Timer A stop. As long as
the prescribed voltage is supplied, the contents of the CPU, some of its on-chip registers and on-
chip RAM are retained, and I/O ports retain their states prior to the transition.
4.8.2

Clearing Subsleep Mode

Subsleep mode is cleared by an interrupt (Timer A interrupt, NMI pin, or pin ,54 to ,54 ), or
by means of the 5(6 pin.
(1) Clearing with an Interrupt
When an interrupt request signal is input, subsleep mode is cleared and interrupt exception
handling is started. Subsleep mode cannot be cleared with an ,54 to ,54 interrupt if the
corresponding enable bit has been cleared to 0, or with an on-chip supporting module
interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable
register or masked by the CPU.
(2) Clearing with the 5(6 Pin
See (2) Clearing with the 5(6 Pin in section 4.6.2, Clearing Standby Mode.
Rev. 2.0, 11/00, page 84 of 1037