Register Configuration - Renesas Hitachi H8S/2194 Series Hardware Manual

15.1.3

Register Configuration

Table 15.1 shows the register configuration of the Timer L. The linear time counter (LTC) and
the reload compare patch register (RCR) are being allocated to the same address.
Reading or writing determines the accessing register.
Table 15.1 Register Configuration
Name
Timer L mode register
Linear time counter
Reload/compare match
register
Note: * Lower 16 bits of the address.
Abbrev. R/W
LMR R/W
LTC R
RCR W
Size Initial Value
Byte H'30
Byte H'00
Byte H'00
Rev. 2.0, 11/00, page 323 of 1037
Address*
H'D112
H'D113
H'D113