Block Diagram - Renesas Hitachi H8S/2194 Series Hardware Manual

20.1.2

Block Diagram

Figure 20.1 shows a block diagram of the 12-bit PWM (1 channel). The PWM signal is
generated by combining quantizing pulses from a 12-bit pulse generator with quantizing pulses
derived from the contents of a data register. Low-frequency components are reduced because
the two quantizing pulses have different frequencies. The error data is represented by an
unsigned 12-bit binary number.
/2
/4
/8
/16
/32
/64
/128
CAPPWM
or
DRMPWM
[Legend]
CAPPWM : Capstan mix pin
DRMPWM : Drum mix pin
Figure 20.1 Block Diagram of 12-Bit PWM (1 channel)
Rev. 2.0, 11/00, page 414 of 1037
PWM control register
Internal data bus
Counter
Pulse generator
Output control circuit
PWM data register
Error data
Digital filter
circuit
· DFUCR
PTON CP/DP