Register Configuration - Renesas Hitachi H8S/2194 Series Hardware Manual

s/2
s/4
RCS
W
Figure 28.7 Block Diagram of CREF Signal Generator
28.3.3

Register Configuration

Table 28.4 shows the register configuration of the reference signal generators.
Table 28.4 Register Configuration
Name
Reference period mode
register
Reference period register 1
Reference period register 2
REF30 counter register
Reference period mode
register 2
Rev. 2.0, 11/00, page 628 of 1037
Counter clear
Counter (16 bit)
Match
Comparator (16 bit)
Reference period register 2 (16 bit)
Reference period buffer 2 (16 bit)
Dummy read
W
Internal bus
Abbrev. R/W
RFM W
RFD W
CRF W
RFC R/W
RFM2 R/W
Clear
Toggle
CRD
W
Size Initial Value
Byte H'00
Word H'FFFF
Word H'FFFF
Word H'0000
Byte H'FE
PB(ASM)
REC
Q S
R
DVCFG2
Edge
CREF
detection
s = fosc/2
Address
H'FD096
H'FD090
H'FD092
H'FD094
H'FD097