Register Descriptions - Renesas Hitachi H8S/2194 Series Hardware Manual

28.13.5 Register Descriptions

(1) CTL Control Register (CTCR)
Bit :
NT/PL
Initial value :
R/W :
The CTL control register (CTCR) controls PB-CTL rewrite and sets the slow mode. When a
CTL pulse cannot be detected with the input amplifier gain set at the CTL gain control register
(CTLGR) in the PB-CTL circuit, bit 1 (UNCTL) of CTCR is set to 1. It is automatically cleared
to 0 when a CTL pulse is detected.
CTCR is an 8-bit readable/writable register. However, bit 1 is read-only, and the rest is write-
only.
CTCR is initialized to H'30 by a reset, and in standby and module stop mode.
Bit 7: NTSC/PAL Selection Bit (NT/PL)
Selects the period of the rewrite circuit.
Bit 7
NT/PL Description
0 NTSC mode (frame rate: 30 Hz)
1 PAL mode (frame rate: 25 Hz)
Bits 6 to 4: Frequency Selection Bits (FSLA, FSLB, FSLC)
These bits select the operating frequency of the CTL rewrite circuit. They should be set
according to fosc.
Bit 6 Bit 5
FSLC FSLB
0 0
1
1
*
Note: Don't care.
*
7 6 5
FSLC FSLB
0 0 1
W W W
Bit 4
FSLA
0
1
0
1
*
4 3
FSLA CCS LCTL
1 0
W W
Description
Reserved (do not set)
Reserved (do not set)
fosc = 8 MHz
fosc = 10 MHz
Reserved (do not set)
Rev. 2.0, 11/00, page 749 of 1037
2 1 0
UNCTL SLWM
0 0 0
W R W
(Initial value)
(Initial value)