Register Descriptions; Watchdog Timer Counter (Wtcnt); Watchdog Timer Control/Status Register (Wtcsr) - Renesas Hitachi H8S/2194 Series Hardware Manual

18.2

Register Descriptions

18.2.1

Watchdog Timer Counter (WTCNT)

Bit : 7
Initial value :
0
R/W :
R/W
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in WTCSR, WTCNT starts counting pulses generated from the
internal clock source selected by bits CKS2 to CKS0 in WTCSR. When the count overflows
(changes from H'FF to H'00), the OVF flag in WTCSR is set to 1.
WTCNT is initialized to H'00 by a reset, or when the TME bit is cleared to 0.
Note: * WTCNT is write-protected by a password to prevent accidental overwriting. For
details see section 18.2.4, Notes on Register Access.
18.2.2

Watchdog Timer Control/Status Register (WTCSR)

Bit :
OVF
Initial value :
R/(W) *
R/W :
Note: * Only 0 can be written to clear the flag.
WTCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source
to be input to WTCNT, and the timer mode.
WTCSR is initialized to H'00 by a reset.
Note: * WTCSR is write-protected by a password to prevent accidental overwriting. For
details see section 18.2.4, Notes on Register Access.
Rev. 2.0, 11/00, page 394 of 1037
6 5
0 0
R/W R/W
7 6 5
WT/IT TME
0 0 0
R/W R/W
4 3
0 0
R/W R/W R/W
4 3
RSTS RST/NMI CKS2
0 0
R/W R/W R/W
2 1 0
0 0 0
R/W R/W
2 1 0
CKS1 CKS0
0 0 0
R/W R/W