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H'D06A: FIFO Timing Pattern Register 2 FTPRB: HSW Timing Generator
Bit :
15
14
FTPRB15 FTPRB14
Initial value :
*
*
R/W :
W
W
Note: * Undetermined
H'D06C: DFG Reference Register 1 DFCRA: HSW Timing Generator
Bit :
7
ISEL2
Initial value :
0
R/W :
W
DFG counter clear bit
Interrupt select bit
0 Interrupt request is generated by clear signal of 16-bit timer counter
1 Interrupt request is generated by VD signal in PB mode
H'D06C: DFG Reference Count Register DFCTR: HSW Timing Generator
7
Bit :
—
1
Initial value :
—
R/W :
H'D06D: DFG Reference Register 2 DFCRB: HSW Timing Generator
Bit :
7
—
Initial value :
1
R/W :
—
Note: * Undetermined
13
12
11
10
FTPRB13 FTPRB12
FTPRB11
FTPRB10
*
*
*
*
W
W
W
W
6
5
CCLR
CKSL
0
0
W
W
16-bit counter clock source select bit
φs/4
0
φs/8
1
0 Normal operation
1 Clear 5-bit DFG counter
6
5
—
—
1
1
—
—
6
5
—
—
1
1
—
—
9
8
7
6
FTPRB9
FTPRB8
FTPRB7
FTPRB6
*
*
*
*
W
W
W
W
4
3
DFCRA4 DFCRA3 DFCRA2 DFCRA1
*
*
W
W
4
3
DFCTR4
DFCTR3
DFCTR2
0
0
R
R
4
3
DFCRB4
DFCRB3
DFCRB2 DFCRB1
*
*
W
W
Rev. 2.0, 11/00, page 935 of 1037
5
4
3
2
FTPRB5
FTPRB4
FTPRB3
FTPRB2
*
*
*
*
W
W
W
W
2
1
DFCRA0
*
*
W
W
2
1
DFCTR1
DFCTR0
0
0
R
R
2
1
DFCRB0
*
*
W
W
1
0
FTPRB1
FTPRB0
*
*
W
W
0
*
W
0
0
R
0
*
W
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