Renesas Hitachi H8S/2194 Series Hardware Manual page 389

IEDGA
Edge detection and
FTIA
capture signal
generating circuit.
Table 17.3 Input Signal Edge Selection when Making Buffer Operation
IEDGA IEDGC
0 0
1
1 0
1
Reading can be made from the ICR through the CPU at 8-bit or 16-bit.
For stable input capturing operation, maintain the pulse duration of the input capture input
signals at 1.5 system clock (φ) or more in case of single edge capturing and at 2.5 system clock
(φ) or more in case of both edge capturing.
The ICR is initialized to H'0000 when reset or under the standby mode, watch mode, subsleep
mode, module stop mode or subactive mode.
Rev. 2.0, 11/00, page 362 of 1037
BUFEA IEDGC
ICRC
Figure 17.2 Buffer Operation (an example)
Selection of the Input Signal Edge
Captures at the rising edge of the input capture input A (Initial value)
Captures at both rising and falling edges of the input capture input A
Captures at the rising edge of the input capture input A
ICRA FRC