Usage Notes - Renesas Hitachi H8S/2194 Series Hardware Manual

16-bit single-chip microcomputer
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25.4

Usage Notes

(1) In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition.
(2) Either of the following two conditions will start the next transfer. Pay attention to these
conditions when reading or writing to ICDR.
(a) Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
(b) Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
ICDRS to ICDRR)
(3) Table 25.5 shows the timing of SCL and SDA output in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, series resistance, and parallel resistance.
2
Table 25.5 I
C Bus Timing (SCL and SDA Output)
Item
SCL output cycle time
SCL output high pulse width
SCL output low pulse width
SDA output bus free time
Start condition output hold time
Retransmission start condition
output setup time
Stop condition output setup time
Data output setup time (master)
Data output setup time (slave)
Data output hold time
Note:
1. 6t
when IICX is 0, 12t
cyc
(4) SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
Electrical Characteristics. Note that the I
be met with a system clock frequency of less than 5 MHz.
Symbol
Output Timing
t
28t
to 256t
SCLO
cyc
t
0.5t
SCLHO
SCLO
t
0.5t
SCLLO
SCLO
t
0.5t
-1t
BUFO
SCLO
t
0.5t
-1t
STAHO
SCLO
t
1t
STASO
SCLO
t
0.5t
+2t
STOSO
SCLO
t
1t
-3t
SDASO
SCLLO
cyc
1t
- (6t
SCLL
t
3t
SDAHO
cyc
when 1.
cyc
, as shown in table 29.6 in section 29,
cyc
2
C bus interface AC timing specifications will not
Unit
ns
cyc
ns
ns
ns
cyc
ns
cyc
ns
ns
cyc
ns
1
or 12t
)
ns
*
cyc
cyc
ns
Rev. 2.0, 11/00, page 567 of 1037
Notes
Figure 28.10
(reference)

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