Block Diagram - Renesas Hitachi H8S/2194 Series Hardware Manual

15.1.2

Block Diagram

Figure 15.1 shows a block diagram of the Timer L.
INTERNAL CLOCK
/128
/64
DVCFG2
PB and
REC-CTL
[Legend]
DVCFG2 : Division signal 2 of the CFG
PB and REC-CTL : Control pluses necessary when making
LMR : Timer L mode register
LTC : Linear time counter
RCR : Reload/compare match register
OVF : Overflow
UDF : Underflow
Rev. 2.0, 11/00, page 322 of 1037
Comparator
reproduction and storage
Figure 15.1 Block Diagram of the Timer L
LMR
LTC
OVF/UDF
Reloading
Match clear
Interrupting
circuit
RCR
Read
Write
Interrupt request