A/D Control Register (Adcr) - Renesas Hitachi H8S/2194 Series Hardware Manual

26.2.3

A/D Control Register (ADCR)

Bit : 7
CK
Initial value :
0
R/W
R/W :
ADCR is a register that sets A/D conversion speed and selects analog input channel. When
executing ADCR setting, make sure that the SST and HST flags in ADCSR is set to 0.
ADCR is an 8-bit readable/writable register that is initialized to H'40 by a reset, and in module
stop mode, standby mode, watch mode, subactive mode and subsleep mode.
Bit 7: Clock Select (CK)
Sets A/D conversion speed.
Bit 7
CK Description
0 Conversion frequency is 266 states
1 Conversion frequency is 134 states
Note: A/D conversion starts when 1 is written in SST, or when HST is set to 1. The conversion
period is the time from when this start flag is set until the flag is cleared at the end of
conversion. Actual sample-and-hold takes place (repeatedly) during the conversion
frequency shown in figure 26.2.
6 5 4
—
HCH1 HCH0
1 0 0
R/W R/W
—
3 2
SCH3 SCH2 SCH1
0 0
R/W R/W R/W
Rev. 2.0, 11/00, page 579 of 1037
1 0
SCH0
0 0
R/W
(Initial value)